Libero IDE User’s Guide
What’s New in Libero IDE v8.6
Probe Insertion
Probe insertion is a post-layout process that enables an IGLOO, ProASIC3 or Fusion FPGA designer to insert probes into the design and bring signals out to package pins on the device in order to evaluate and debug the design. During testing of a programmed device, a situation might occur where the device logic is not behaving as expected. Probe insertion enables designers to select internal nets anywhere in the design, connect signals to unused pins, and then run incremental layout.
Net(s) selection and probe assignments are made by using the Generate Probed Design feature available from the Designer Tools menu. If all package pins are already assigned, you can temporarily disconnect a used pin, and connect the probed signal to that pin. The re-routed design can then be programmed into the FPGA, where an external logic analyzer or oscilloscope can be used to view the activity of the probed signal.
Once the evaluation is complete, you can use the original saved layout file if no design modifications are needed, or otherwise make the necessary modifications to the design and re-run layout. Probe insertion has a minimal effect on the overall design and is a convenient way to quickly understand logic issues in your design.
SmartPower
A Monte Carlo computational algorithm supports a new Vectorless Estimation of design activity. Vectorless Estimation is an alternative to the traditional fixed toggle rate default estimation methodology used in SmartPower. Vectorless methodology improves the power consumption results typically to within +/- 10% of that achieved with a simulation derived Value Change Dump (VCD) file method, requiring a substantially shorter run-time. With this new vectorless approach, a VCD file is not needed.
Test results show that power estimation accuracy is near that of a VCD generated analysis and is typically accomplished within the normal start-up time of SmartPower. Monte Carlo Vectorless Estimation is used by default in SmartPower for new designs. Designs in process that already have committed SmartPower settings will use the saved settings. For the most accurate power report Actel recommends using a simulation-driven VCD file.
An I/O Advisor analyzes Output Load, Drive Strength, and Slew Rate settings in a design, and provides anopportunity to input or select alternative settings to reduce the power consumption of I/Os. For Drive Strength and Slew Rates, alternate suggested values are shown if an improvement is possible. The I/O Advisor analyzes power based on existing timing constraints, pointing out positive and negative timing slacks. Adjustments can be made to improve negative slacks and/or balance slacks in the interest of lowering power. The I/O advisor provides an opportunity to input “what-if” values for Output Load, Drive Strength, and Slew Rates and understand in real time the impact on your I/O timing and power.
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